1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No 2009-231725, filed Oct. 5, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
With the miniaturization of semiconductor devices, the gate length of MOS transistors has been reduced. Regarding planar MOS transistors, the reduction in the gate length causes the short channel effect. Consequently, the threshold voltage is reduced, thereby causing an increase in off-current.
Japanese Patent Laid-Open Publication No. 2007-158269 discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel portion between an STI (Shallow Trench Isolation) region and a gate trench. Japanese Patent Laid-Open Publication No. 2007-258660 discloses a semiconductor device including a recessed channel region and a method of manufacturing the same.
The semiconductor devices of the above related art include a recessed channel region between a recessed gate electrode and an element isolation region. Hereinafter, such transistors as disclosed in the above related art are referred to as RC (Recessed Channel) transistors.
Japanese Patent Laid-Open Publication No. H09-232535 discloses a method of manufacturing a semiconductor device in which a photolithography process for forming a trench and a photolithography process for forming a gate electrode are carried out in one process. Compared to the trench gate transistor, which is formed by simply embedding a gate electrode in a trench, the RC transistor is a higher performance transistor that can prevent a decrease in the threshold voltage and increase the on-current as much as possible.
The operation characteristics of the RC transistor vary according to the shape and height of the channel region adjacent to a side surface of the recess. It is important to optimize the shape and height of the channel region of the RC transistor according to the electrical characteristics required for a device to which the RC transistor is applied.
Regarding the methods of the related art, however, it has been difficult to precisely adjust and properly process the shape and height of the channel region. Further, a bur portion is likely to remain. The bur portion is a thin semiconductor layer, which covers a side surface of the element isolation region. For this reason, it has been difficult to remove the bur portion while maintaining the shape and height of the channel region.
Japanese Patent Laid-Open Publication No. 2007-194333 discloses a method of removing a bur portion (Si bur) which remains and covers a side surface of an element isolation region of a trench gate transistor. The bur portion affects operations of the trench gate transistor. However, an object of the method is to completely remove the bur portion or to reduce the size of the bur portion to 10 nm or less. For this reason, the amount of the removed silicon substrate is so large. Therefore, the method of the related art cannot be applied to an RC transistor including, as a channel region, a semiconductor layer forming a Si bur portion.
Thus, according to the methods of the related art, it has been difficult to adjust the height of the channel region of the RC transistor to be in a desired range. Further, it has been difficult to completely remove the bur portion remaining adjacent to the channel region.